Abrupt metal-insulator transition device with parallel conducting layers

ABSTRACT

An abrupt MIT (metal-insulator transition) device with parallel conducting layers is provided. The abrupt MIT device includes a first electrode disposed on a certain region of a substrate, a second electrode disposed so as to be spaced a predetermined distance apart from the first electrode, and at least one conducting layer electrically connecting the first electrode with the second electrode and having a width that allows the entire region of the conducting layer to be transformed into a metal layer due to an MIT. Due to this configuration, deterioration of the conducting layer, which is typically caused by current flowing through the conducting layer, is less likely to occur.

TECHNICAL FIELD

The present invention relates to a device using a metal-insulatortransition (MIT) effect, and more particularly, to a device using anabrupt MIT material as a conductor whose phase can be transformed into ametal.

BACKGROUND ART

As is generally known, an MIT occurs at a Mott insulator and a Hubbardinsulator. The Hubbard insulator is a consecutive MIT. A field effecttransistor (FET) that uses the Hubbard insulator as a channel layer wasintroduced in an article by D. M. Newns et al., Appl. Phys. Lett., vol.73, p. 780, 1998. Since the Hubbard insulator uses an MIT that occursconsecutively, charges to be used as a carrier need to be addedconsecutively until an excellent metallic characteristic is achieved.

An article by Hyun-Tak Kim, NATO Science Series Vol. II/67, Kluwer, p.137, 2002, which is also described on the web sitehttp://xxx.lanl.gow/abs/cond-mat/0110112, teaches a theory that supportsan abrupt MIT due to the Mott insulator. According to the theory in theabove article, the Mott insulator has a bounded and metallic electronstructure. Energy between electrons of the Mott insulator is made tochange, and thus, an insulator-to-metal transition does not occurconsecutively; rather it occurs abruptly. Changing temperature, pressureor an electric field instigates the energy change between the electronsof the Mott insulator. For instance, when holes with a low dopingdensity are added to the Mott insulator, the insulator-to-metaltransition occurs abruptly or suddenly.

In a typical abrupt MIT device, when an inconsecutive MIT occurs, alarge amount of current flows abruptly. Thus, a conducting layer is morelikely to be deteriorated. FIG. 1 illustrates a top view of a typicalMIT device 10.

The typical MIT device 10 includes a pair of electrodes 14 and 16arranged to be spaced a predetermined distance apart from each other oncertain regions of a substrate 12. An MIT material layer is disposedbetween the pair of the electrodes 14 and 16. The MIT material layermakes an electric connection between the electrodes 14 and 16 and causesan abrupt MIT. The abrupt MIT causes the MIT material layer to betransformed into a metal layer. Hence, the MIT material layer can beused as a conducting layer 18. The conducting layer 18 has a width of‘W’.

FIG. 2 illustrates a top view of a sample 20 analyzed by micro-Ramanspectroscopy to check structural uniformity of the conducting layer 18of the typical MIT device 10 (FIG. 1). FIG. 3 illustrates a graph of theintensity as a function of the Raman shift for the conducting layer 18illustrated in FIG. 2. As is well known, Raman spectroscopy is used toobserve vibration energy of lattices. For metal, a peak is not observed.The width W of the conducting layer 18 is exaggerated for clarity.

The sample 20 includes the conducting layer 18 disposed on a support 22and an analytical electrode 24 segmented into a certain number ofregions and contacting the conducting layer 18. For instance, theanalytical electrode 24 is segmented into three regions including anupper region 24A, a central region 24B and a lower region 24C and has aprotruding structure. In FIG. 3, the intensity as a function of theRaman shift, which is typically reported in units of cm⁻¹, shows thecharacteristics of a substrate, more particularly, a region arepresenting Al₂O₃ and regions b and c measured when a large amount ofcurrent, e.g., a current amount of ‘F’ as marked in FIG. 8, flowsthrough the conducting layer 18. The curvature regions b and c are themeasurements at the central region 24B (see FIG. 2) and at the upper andlower regions 24A and 24C (see FIG. 2), respectively. Reference numeral35 represents a peak indicating Al₂O₃. Scattered Raman peaks indicatethat a phase of the conducting layer 18 is not yet transformed into ametal state. Therefore, the MIT does not yet take place at the upperregion 24A and the lower region 24C, and continues to remain in aninsulator state. The central region 24B has a phase transition to metal.The conducting layer 18 that includes an insulator region is called anon-uniform conducting layer. However, an MIT material to be used as theconducting layer 18 usually needs to be uniform. That is, the conductinglayer needs to be a uniform conducting layer that is entirelytransformed into a metal layer after the MIT.

Due to several limitations in typical fabrication methods, theconducting layer is often non-uniform in actual industrial practice. Forinstance, the inventors of this patent application reported thisexemplary case in New J. Phys. Vol. 6, p. 52, 2004. It wasexperimentally verified that the conducting layer 18 was easilydeteriorated due to the non-uniformity characteristic. In detail, thenon-uniform conducting layer 18 was easily deteriorated due to heatgenerated by a large amount of current.

In order to implement an MIT in other application fields, a large amountof current needs to flow uniformly after a phase transition from aninsulator to a metal occurs. Hence, it is generally essential to developa uniform conducting layer. A method of reducing the deterioration of aconducting layer when current flows through an MIT device has not yetbeen developed.

DISCLOSURE OF INVENTION Technical Problem

The present invention provides an abrupt MIT device that can reducedeterioration of a conducting layer when current flows through theconducting layer.

Technical Solution

According to an aspect of the present invention, there is provided anabrupt MIT device, including a first electrode disposed on a certainregion of a substrate, a second electrode disposed so as to be spaced apredetermined distance apart from the first electrode, and at least oneconducting layer electrically connecting the first electrode with thesecond electrode and having a width that allows the entire region of theconducting layer to be transformed into a metal layer due to an MIT.

The abrupt MIT device may further include a gate electrode configured toextend over a certain region of the conducting layer and have a gateinsulation layer interposed between the conducting layer and the gateelectrode. The conducting layer, the first electrode and the secondelectrode may be configured to become parts of a protection circuit. Theabrupt MIT device may further include an electrical system connected inparallel with the protection circuit.

DESCRIPTION OF DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent by describing in detail exemplary embodimentsthereof with reference to the attached drawings in which:

FIG. 1 illustrates a top view of a typical MIT device including twoterminals configured in a horizontal structure;

FIG. 2 illustrates a top view of a sample analyzed by micro-Ramanspectroscopy to check structural uniformity of a conducting layer of atypical MIT device;

FIG. 3 illustrates a graph of the intensity as a function of the Ramanshift for the conducting layer illustrated in FIG. 2;

FIG. 4 illustrates a top view of an MIT device including two terminalsconfigured in a horizontal structure, according to an embodiment of thepresent invention;

FIG. 5 illustrates a top view of an MIT device including three terminalsconfigured in a horizontal structure, in which a gate insulator isformed on a conducting layer, according to another embodiment of thepresent invention;

FIG. 6 illustrates a top view of an MIT device including three terminalsconfigured in a horizontal structure, in which a gate insulator isformed below a conducting layer, according to another embodiment of thepresent invention;

FIG. 7 illustrates a top view of an MIT device including three terminalsconfigured in a horizontal structure, in which a conducting layer isformed on a gate insulator, according to another embodiment of thepresent invention;

FIG. 8 illustrates a graph of current (I) versus voltage (V) applied toa conducting layer according to an embodiment of the present invention;

FIG. 9 is a circuit diagram illustrating a protection circuit, anequivalent load R_(L) and a power supply voltage V_(p) terminalaccording to an embodiment of the present invention; and

FIG. 10 illustrates a graph of voltage of an MIT device versus time forwhich the power supply voltage V_(p) terminal illustrated in FIG. 9supplies a voltage of approximately 1,500 V according to an embodimentof the present invention.

BEST MODE

The present invention will now be described more fully with reference tothe accompanying drawings, in which exemplary embodiments of theinvention are shown. The invention may, however, be embodied in manydifferent forms and should not be construed as being limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the concept of the invention to those skilled in the art. Likereference numerals denote like elements even in different drawings.

A conducting layer that is entirely transformed into a metal layer dueto an MIT and MIT devices using the conducting layer according tovarious embodiments of the present invention will be described below indetail. The conducting layer has a path where current can flow, and inparticular, conducting layers according to various embodiments of thepresent invention can be transformed into a metal layer across theirentire width. As described in FIG. 3, the conducting layer does not havethe scattered Raman peak, and more particularly, current needs to flowuniformly to the conducting layer.

The conducting layer according to various embodiments of the presentinvention includes a material that can undergo an abrupt MIT. Thus, adevice using the conducting layer can be referred as to an MIT device.The MIT device can be modified into various forms within the scope andsprit of the present invention. The illustrated MIT devices areexemplary embodiments.

FIG. 4 illustrates a top view of an MIT device 100 including twoterminals configured in a horizontal structure according to anembodiment of the present invention.

As illustrated, at least one conducting layer 110 is disposed between afirst electrode 104 and a second electrode 106 that are arranged so asto be spaced a pre-determined distance apart from each other overcertain regions of a substrate 102. The conducting layer 110 makes anelectric connection between the first electrode 104 and the secondelectrode 106, and in the present embodiment, multiple conducting layers110 are formed. Each of the conducting layers 110 has a region having awidth W₁, W₂ or W₃, at which the individual conducting layers 110 can betransformed into metal layers due to an MIT. If there are multipleconducting layers 110, the conducting layers 110 may be electricallyconnected in parallel. Although not illustrated, a buffer layer mayfurther be disposed between the substrate 102 and the conducing layer110. The buffer layer may be disposed over the entire substrate 102.

The conducting layer 110 may include one selected from a groupconsisting of an inorganic compound semiconductor and an insulator, anorganic semiconductor and an insulator, a semiconductor, and anoxide-based semiconductor and an insulator. The inorganic compoundsemiconductor includes one selected from a group consisting of oxygen,carbon, semi-conductive elements from groups III to V or groups II toVI, transition metal elements, rare-earth elements, and lanthanum-basedelements, and holes with a low doping density are added thereto. Holeswith a low doping density are also added to the organic semiconductor,and the insulator the semiconductor, and the oxide-based semiconductorand the insulator.

The entire region of the conducting layer 110 having the set width istransformed into a metal layer, and thus, the Raman peak is notobserved. Also, current needs to flow uniformly throughout theconducting layer 110. If the current flow is uniform throughout theconducting layer 110, heat generation caused by resistance can bereduced. As a result, the conducting layer 110 can be formed morestably.

The current flowing through the conducting layer 110 is substantiallythe same as the sum of the areas of the multiple conducting layers 110,and the amount of current may be at least two times larger than that ofthe current flowing through the conducting layer 18 that has the Ramanpeak as described in FIG. 3. For instance, assuming that one conductinglayer including the Raman peak (i.e., the non-uniform conducting layer)has a width W, this conducting layer can be segmented into multipleconducting layers 110, each having a width W₁, W₂ or W₃ as described inthe present embodiment. Although FIG. 3 illustrates three conductinglayers 110, which are uniform conducting layers, as an example, variousnumbers of conducting layers 110 may be formed as need requires. Theconducting layer 110 according to the present embodiment is a uniformconductor. Thus, a larger current amount can flow thereto as comparedwith the current amount flowing to the typical non-uniform conductinglayer. A parallel connection of the multiple conducting layers 110allows a current flow to increase to a greater extent.

Each of the first electrode 104 and the second electrode 106 may includeone selected from a group consisting of a metal group, a compound ofmetals selected from the metal group, and an oxide-based materialincluding one metal from the metal group and the compound. The metalgroup includes Li, Be, C, Na, Mg, Al, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co,Ni, Cu, Zn, Ga, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn,Sb, Cs, Ba, La, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Pb, Bi, Po, Ce, Pr,Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Th, U, Np, and Pu.

A protection electrode 108 being resistant to heat, which may begenerated by current flowing to the conducting layer 110, may be furtherformed between the conducting layer 110 and the first electrode 104 andbetween the conducting layer 110 and the second electrode 106. Since theconducting layer 110 illustrated in FIG. 1 may be realised as multipleconducting layers 110, multiple protection electrodes 108 may also beformed. The protection electrode 108 may include one selected from agroup consisting of a metal group, a compound of metals selected fromthe metal group, and an oxide-based material including one metal fromthe metal group and the compound. The metal group includes Li, Be, C,Na, Mg, Al, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Rb, Sr, Y,Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, Hf, Ta, W,Re, Os, Ir, Pt, Au, Hg, Pb, Bi, Po, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho,Er, Tm, Yb, Lu, Th, U, Np, and Pu.

Although the substrate 102 is not limited to a specific material, thesubstrate 102 may include one selected from a group consisting of anorganic layer, an inorganic layer, at least one multi-layer includingmultiple layers of the organic layer and the inorganic layer, and apatterned structure thereof. For instance, the substrate 102 may beformed using various materials such as single crystal sapphire, silicon,glass, quartz, compound semiconductors, and plastic materials. In thecase of using glass or plastic materials, a reaction temperature islimited. Using a plastic material allows the substrate 102 to beflexible. Silicon, glass and quartz are advantageous when the substrate102 is required to have a diameter of 8 inches or more. The substrate102 may also have a silicon on insulator (SOI) structure to satisfy therequirement.

The buffer layer is formed to improve crystallinity and adhesiveness.The buffer layer may include a crystalline thin film that has a similarlattice constant to the conducting layer 110. For instance, the bufferlayer may be formed of one selected from a group consisting of aluminiumoxide, high-k dielectric materials, crystalline metal, and siliconoxide. An aluminium oxide layer that can maintain a certain level ofcrystallinity is sufficient, and the silicon oxide layer is formed asthin as possible. In particular, the buffer layer may be formed inmultiple layers including high-k dielectric layers with excellentcrystallinity, mixture layers thereof, and/or crystalline metal layers.TiO₂, ZrO₂, Ta₂O₅, and HfO₂ layers are examples of the high-k dielectriclayers.

In a device with two terminals, as the conducting layer 110 istransformed into a metal layer, current flows in a direction horizontalto the substrate 102. Although not described in detail, the conductinglayer can be applied to a device with two terminals configured in avertical structure, in which current flows in the direction vertical tothe substrate 102.

FIGS. 5 through 7 illustrate top views of respective MIT devices 210,220, and 230 according to other embodiments of the present invention.Devices with three terminals configured in a horizontal structure areexemplified below in the other embodiments of the present invention. Thesame reference numerals represent the same elements described in FIG. 4,and thus, detailed description thereof will be omitted.

As illustrated in FIG. 5, the device with the three terminals (i.e., MITdevice 210) may be configured such that a gate insulation layer 202 isdisposed over conducting layers 110, and a third electrode 204 extendsover a certain region of the gate insulation layer 202. As illustratedin FIG. 6, another device with three terminals (i.e., the MIT device220) may be configured such that a fourth electrode 214 is disposedbetween a substrate 102 and conducting layers 110, and the fourthelectrode extends over certain regions of the conducting layers 110 witha gate insulation layer 212 formed between the fourth electrode 214 andthe conducting layers 110. FIG. 5 illustrates a device structure inwhich the third gate electrode 204 is disposed on top of the conductinglayers 110. In contrast, FIG. 6 illustrates a device structure in whichthe fourth gate electrode 214 is disposed underneath the conductinglayers 110.

FIG. 7 illustrates a device structure that is substantially the same asthe device structure illustrated in FIG. 6 except for the shape of aconducting layer 222. The conducting layer 222 may be configured tocover an entire region between a first electrode 104 and a secondelectrode 106. The conducting layer 222 has a width Wf that allows theentire region of the conducting layer 222 to be transformed into a metallayer due to an MIT. Unlike the conducting layers 110 illustrated inFIGS. 5 and 6, the conducting layer 222 is not segmented. When anelectric field is applied, a conductive channel of the conducting layer222 is formed along a region having the shortest distance between thefirst electrode 104 and the second electrode 106. Thus, the device withthe three terminals illustrated in FIG. 7 may operate similarly to thedevice with the three terminals illustrated in FIG. 5 or 6.

The gate insulation layers 202 and 212 illustrated in FIGS. 5 through 7cover one surface region of each of the conducting layers 110 and 222because of the following reason. Since the conducting layers 202 and 212are already transformed into metal layers, as known, current flows tothe surfaces of the conducting layers 110 and 222 due to a surfaceeffect. If necessary, an amount of current flowing to the conductinglayer 110 or 222 contacting the gate insulation layer 202 or 212 can beadjusted by covering exposed surface regions of the conducting layer 110or 222, e.g., upper surfaces and both side surfaces of the conductinglayers 110 illustrated in FIG. 5.

FIGS. 5 through 7 show various exemplary implementations of the devicewith the three terminals using the single or multiple conducing layersaccording to the embodiments of the present invention. Therefore, theconducting layers can be applicable to those devices with threeterminals configured in various structures without departing from thescope and spirit of the present invention.

FIG. 8 illustrates a graph of current (I) versus voltage (V) of aconducting layer according to an embodiment of the present invention.The conducting layer has a length L of approximately 15 μm. Multipleconducting layers are formed (i.e., a segmented conducting layer). Inthis embodiment, the conducting layer is segmented into 10 regions, eachhaving a width of approximately 10 μm, and the 10 segmented regions ofthe conducting layer are connected in parallel to have a total width Wof approximately 150 μm. Reference denotations □, ◯, and Δ represent thenumber of tests performed, e.g., one time, two times and three times,respectively.

As illustrated, the conducting layer has a critical voltage e at whichan abrupt electric characteristic of the conducting layer changesabruptly from an insulator d to a metal state f. In the presentembodiment, the critical voltage of the conducting layer when it hasundergone an abrupt transition is approximately 13 V. In more detail,when the voltage of the conducting layer is in a voltage range fromapproximately 0 V to 13 V, the conductive layer is in an insulator stated in which current barely flows, and when the voltage of the conductivelayer is greater than approximately 13 V, the conducting layer is in themetal state f. In other words, abruptly current jump occurs at a voltageof approximately 13 V. At this time, when the conducting layer is in ametal state f, it contains lots of electrons. The critical voltage,i.e., the electrical characteristic of the conducting layer, may varydepending on a device structure including an abrupt MIT material layerand the type of material layer used.

FIG. 9 is an exemplary circuit diagram illustrating a protection circuit300, an equivalent load R_(L) and a power supply voltage V_(p) terminalaccording to an embodiment of the present invention.

The protection circuit 300 is configured to remove static electricityapplied to the equivalent load R_(L) through a terminal to which thepower supply voltage V_(p) is supplied or to remove high voltage andhigh frequency noise. The protection circuit 300 is configured with anMIT device, e.g., the device with the two terminals illustrated in FIG.4, and a protection resistor R_(p) that are connected in parallel. Theprotection resistor R_(p) limits a voltage or current to a certain levelor amount applied to the MIT device in order to protect the MIT device.

FIG. 10 illustrates a graph of voltage versus time for which power issupplied from the power supply voltage V_(p) terminal illustrated inFIG. 9. In a voltage range from approximately 250 V to 1,000 V, avoltage of the MIT device was measured for every 50 V. In a voltagerange from approximately 1,000 V to 1,500 V, the voltage of the MITdevice was measured for every 100 V. The measured voltage level at eachmeasuring point is labelled with small circles ◯. The conducting layerillustrated in FIG. 8 was used. More specifically, the conducting layerhad a length L of approximately 15 μm and a total width of approximately150 μm attained by making a parallel connection between the 10 segmentedregions of the conducting layer, each having a width of approximately 10μm.

As illustrated, when the power supply voltage V_(p) terminal supplies avoltage of approximately 1,500 V for approximately 10⁻⁹ seconds, the MIToccurs at the conducing layer. As a result, most of the current flows tothe conducting layer. Due to the resistance of the protection circuit300, the level of residual voltage is approximately 800 V, and theremaining voltage of approximately 1320 V is supplied to the equivalentload R_(L), namely a load resistor. However, when the voltage suppliedto the load resistor R_(L), current flows barely. Thus, damage to theload resistor R_(L), usually caused by the power supply voltage V_(p),can be reduced. The power supply voltage V_(p) may be noise suppliedthrough the terminal.

As is known in the art, the current conducting capability of theprotection circuit increases as the resistance of the conducting layerdecreases. After the MIT, the conducting layer according to theembodiments of the present invention can conduct a larger amount ofcurrent than the typical non-uniform conducting layer including aninsulator structure. Since the conducting layer according to theembodiments of the pre sent invention is a uniform conductor, a currentflow increases to a greater extent as compared with the non-uniformconducting layer. An appropriate parallel connection of the segmentedregions of the conducting layers allows a much larger amount of currentto flow as compared with other conducting layers.

According to the embodiments of the present invention, the abruptMIT-based device uses at least one conducting layer having a region thatcan be entirely transformed into a metal layer after the MIT. Thus, itis possible to reduce deterioration of the conducting layer due to heat,typically generated by a large amount of current flowing through theconducting layer.

Furthermore, connecting the multiple conducting layers in parallelallows appropriately adjusting an amount of current flowing through theconducting layers.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

1. An abrupt MIT (metal-insulator transition) device comprising: atleast one conducting layer having a width that allows the entire regionof the conducting layer to be transformed into a metal layer due to anMIT.
 2. The abrupt MIT device of claim 1 further comprising: a firstelectrode disposed on a certain region of a substrate; and a secondelectrode disposed so as to be spaced a predetermined distance apartfrom the first electrode; wherein the conducting layer electricallyconnecting the first electrode with the second electrode.
 3. The abruptMIT device of claim 2, wherein the first electrode and the secondelectrode are spaced a predetermined distance from each other andpartially cover both the first and second sides of the MIT insulator. 4.The abrupt MIT device of claim 2 wherein the first electrode and thesecond electrode are disposed with the MIT insulator therebetween andentirely cover both the first and second sides of the MIT insulator. 5.The abrupt MIT device of claim 1, wherein if the conducting layer isrealized as a plurality of conductive layers, the conducting layers areelectrically connected in parallel.
 6. The abrupt MIT device of claim 1,wherein the conducting layer includes one selected from a groupconsisting of an inorganic compound semiconductor and an insulator, anorganic semiconductor and an insulator, a semiconductor, and anoxide-based semiconductor and an insulator, wherein the inorganiccompound semiconductor includes one selected from a group consisting ofoxygen, carbon, semi-conductive elements from groups III to V or groupsII to VI, transition metal elements, rare-earth elements, andlanthanum-based elements, and holes with a low doping density are addedto the inorganic compound semiconductor and the insulator; and holeswith a low doping density are added to the organic semiconductor and theinsulator, the semiconductor, and the oxide-based semi-conductor and theinsulator.
 7. The abrupt MIT device of claim 1, wherein current flowsuniformly to the entire region of the conducting layer.
 8. The abruptMIT device of claim 2, wherein each of the first electrode and thesecond electrode includes one selected from a group consisting of ametal group, a compound of metals selected from the metal group, and anoxide-based material including one metal from the metal group and thecompound, wherein the metal group includes Li, Be, C, Na, Mg, Al, K, Ca,Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Rb, Sr, Y, Zr, Nb, Mo, Tc,Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, Hf, Ta, W, Re, Os, Ir, Pt,Au, Hg, Pb, Bi, Po, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu,Th, U, Np, and Pu.
 9. The abrupt MIT device of claim 2, furthercomprising a protection electrode disposed between the conducting layerand the first electrode and between the conducting layer and the secondelectrode and resistant to heat generated by current flowing through theconducting layer.
 10. The abrupt MIT device of claim 9, wherein theprotection electrode includes one selected from a group consisting of ametal group, a compound of metals selected from the metal group, and anoxide-based material including one metal from the metal group and thecompound, wherein the metal group includes Li, Be, C, Na, Mg, Al, K, Ca,Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Rb, Sr, Y, Zr, Nb, Mo, Tc,Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, Hf, Ta, W, Re, Os, Ir, Pt,Au, Hg, Pb, Bi, Po, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu,Th, U, Np, and Pu.
 11. The abrupt MIT device of claim 2, furthercomprising a gate electrode configured to extend over a certain regionof the conducting layer and have a gate insulation layer interposedbetween the conducting layer and the gate electrode.
 12. The abrupt MITdevice of claim 11, wherein the gate insulation layer covers at leastone surface region of the conducting layer.
 13. The abrupt MIT device ofclaim 11, further comprising a third electrode configured to extend overa certain region of the conducting layer and have a gate insulationlayer interposed between the conducting layer and the third electrode.14. The abrupt MIT device of claim 11, further comprising a thirdelectrode configured to extend over the conducting layer and have a gateinsulation layer interposed between the conducting layer and thesubstrate.
 15. The abrupt MIT device of claim 11, further comprising athird electrode configured to extend over the conducting layer and havea gate insulation layer interposed between the conducting layer and thesubstrate, wherein the conducting layer covers an entire region betweenthe first electrode and the second electrode.
 16. The abrupt MIT deviceof claim 2, wherein the conducting layer, the first electrode and thesecond electrode are configured to become parts of a protection circuit,and the abrupt MIT device further comprises an electrical systemconnected in parallel with the protection circuit.
 17. The abrupt MITdevice of claim 16, wherein the protection circuit takes in most of thecurrent due to the abrupt MIT.
 18. The abrupt MIT device of claim 16,wherein the electrical system is protected by conducting most of thecurrent through the protection circuit.